FIG. 1 shows a typical eight-by-eight core array. The X-axis drive wire carries a half-select "read" or "write" current pulse equivalent to one-half the current required to switch a core. The Y-axis drive wire also carries a half-select "read" or "write" current pulse. Either half-select pulse is insufficient to switch a core. The sense/inhibit wire carries a half-select current pulse during the "write" operation, and also carries the sense voltage during the "read" operation.
During the "write" operation, when a ONE is to be written, half-select current pulses are driven along the X and Y wires and add at the selected address to change the flux state of the core. When a core is to be left in the ZERO state, X and Y lines again receive half-select current pulses, but at the same time a half-select current pulse is driven along the sense/inhibit wire. The direction of this pulse opposes and therefore cancels the X pulse. The net result is one half-select pulse which is insufficient to switch the core; as a result, the core remains in a ZERO state.
During the "read" operation, X and Y half-select current pulses are again applied, but in the opposite direction. These current pulses add at the core location to switch the core. The sense/inhibit wire functions during this portion of the cycle to carry the sense voltage to the differential sense amplifier.
The technique of using one wire for both the sense and inhibit functions involves splitting the sense/inhibit winding into two wires or legs (FIG. 2), and driving the inhibit current into each leg. Only one inhibit-driver circuit, hereinafter referred to as a "digit driver" is required for the two legs. The bisecting of the wire results in a shorter period of time required for transient decay.
In addition, the use of a differential sense amplifier for detection of the signal provides a means of eliminating noise transients. This amplifier has a high common-mode rejection that combines and rejects the major part of the common mode noise. The circuit and memory operation just described is disclosed in the publication "Computer Design", July, 1968, page 50.
Multiple digit drivers are presently used in conventional coincident current core memories for producing a relatively large amplitude current pulse with controlled transient and steady state characteristics. These drivers control the data content to be written into core memory and to a large extent influence memory speed and performance.
Digit driver electrical characteristics are very critical, especially during turn-off in three-wire-3D coincident current core memory systems where a single winding is shared for both the sense and inhibit functions for each digit of the memory word. A subsequent memory read cycle cannot be successfully performed until the common sense/digit lines have fully recovered from the efforts of the previous large amplitude digit current pulses. During the memory read cycle, a relatively small core switching voltage appears across the common sense/digit lines for each digit of the memory word which is sensed and interrogated by corresponding sense amplifiers to determine data content.